1. Field of the Disclosure
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors having complex dopant profiles and including a silicon/germanium alloy for creating strain in the channel region.
2. Description of the Related Art
Integrated circuits comprise a large number of circuit elements on a given chip area according to a specified circuit layout, wherein transistors, such as field effect transistors, represent an important component that is used as switching element, current and/or voltage amplifier. The transistors are formed in and above substantially crystalline semiconductor regions with additional dopant materials that are formed at specified substrate locations to act as “active” regions, that is, to act, at least temporarily, as conductive areas for creating a controlled current flow. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A transistor, irrespective of whether an N-channel transistor or a P-channel transistor or any other transistor architecture is considered, comprises so-called PN junctions that are formed by an interface of highly doped regions, such as drain and source regions, with a lightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In the case of a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region substantially affects the performance of the MOS transistors. Thus, the scaling of the channel length, and associated therewith the reduction of channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, entails a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the dimensions of transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity, in combination with a desired channel controllability, in order to counter so-called short channel effects, such as drain-induced barrier lowering and the like. In addition, the vertical location of the PN junctions with respect to the gate insulation layer also represents a critical design criterion in view of leakage current control, as reducing the channel length also requires reducing the depth of the drain and source regions with respect to the interface formed by the gate insulation layer and the channel region, thereby calling for sophisticated implantation techniques.
Furthermore, since the continuous size reduction of the critical dimensions, e.g., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified process steps, it has been proposed to also enhance device performance of the transistor elements by increasing the charge carrier mobility, for instance, in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node of down-sized devices while avoiding many of the above process adaptations associated with device scaling. In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, in field effect transistors, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, thereby presently making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in respective semiconductor regions, such as the channel region, may be dilated/stretched, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region of a field effect transistor with respect to the current flow direction increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials and manufacturing techniques.
Consequently, it has been proposed to introduce a silicon/germanium alloy in the drain and source regions of P-channel transistors to create compressive stress that may result in a corresponding strain.
With reference to FIGS. 1a-1c, typical conventional approaches will be described for enhancing performance of P-channel transistors with respect to reducing short channel effects, enhancing charge carrier mobility in the channel region and reducing overall series resistance of the drain/source path.
FIG. 1a schematically illustrates a cross-sectional view of a P-channel transistor 100 including a substrate 101, such as a silicon bulk substrate and a silicon-on-insulator (SOI) substrate, i.e., a buried insulating layer (not shown) may be formed on the substrate 101. Furthermore, a semiconductor layer 102, such as a silicon layer, is formed above the substrate 101 and may include isolation structures 103, such as shallow trench isolations and the like. The isolation structures 103 may define an “active” region in and above which one or more transistor elements may be formed, such as the transistor 100. It should be appreciated that an active region is to be understood as a semiconductor region receiving or having formed therein appropriate dopant profiles so as to adjust the overall conductivity in accordance with device requirements, for instance for achieving transistor characteristics and the like. In the manufacturing stage shown, a gate electrode structure 104 may be formed above the semiconductor layer 102, wherein a gate insulation layer 104A of the gate electrode structure 104 separates a gate electrode material, such as polysilicon and the like, from a channel region 105 in the semiconductor layer 102. Moreover, as illustrated, the gate electrode structure 104 may have formed on sidewalls thereof a non-electrode material in the form of spacer elements 104B, such as silicon dioxide and the like. Furthermore, the gate electrode structure 104 is encapsulated by spacer elements 107 and a cap layer 108, which may, for instance, be comprised of silicon nitride. Furthermore, recesses or cavities 106 are formed in the semiconductor layer 102 laterally adjacent to and offset from the gate electrode structure 104, wherein a lateral offset is substantially determined by the width of the spacer 104B and the spacer 107.
A typical conventional process flow for forming the transistor 100 as shown in FIG. 1a may comprise the following processes. After forming the isolation structures 103, an appropriate vertical dopant profile within the semiconductor layer 102 may be defined by accordingly designed implantation processes. Thereafter, material layers for the gate electrode structure 104, i.e., a gate dielectric material and an electrode material, may be formed by appropriate techniques, such as thermal or wet chemical oxidation and/or deposition for the gate dielectric, while frequently low pressure chemical vapor deposition (LPCVD) may be used for depositing polysilicon as a gate electrode material. Moreover, further material layers, such as material for the cap layer 108, which may act as a portion of an anti-reflective coating (ARC), may also be deposited in accordance with well-established process recipes. The resulting layer stack may then be patterned by advanced photolithography and etch techniques, followed by the formation of the spacer 104B, for instance by thermal oxidation, deposition and the like. Next, a spacer material may be deposited, for instance in combination with a liner material, if required, which may then be patterned by well-established anisotropic etch techniques to obtain the spacer elements 107, the width of which may substantially determine the lateral offset of the cavities 106.
As previously explained, uniaxial compressive strain in the channel region 105 in the current flow direction may significantly enhance the mobility of holes, thereby enhancing overall performance of the transistor 100 when representing a P-channel transistor. In order to provide the desired compressive strain, the cavities 106 may be formed by well-established etch techniques using the spacers 107 and the cap layer 108 as an etch mask, wherein, in the example shown, the isolation structures 103 may also act as an etch mask. In other cases, an additional hard mask layer may be provided if the lateral extension of the cavities 106 is to be restricted so as to not entirely extend to the isolation structures 103. During the corresponding etch process, a certain amount of template material of the layer 102 may also be maintained if an SOI configuration is considered, in which a buried insulating layer may be positioned between the substrate 101 and the semiconductor layer 102. The cavities 106 may be refilled with an appropriate semiconductor material, such as silicon/germanium alloy, which has a natural lattice constant that is greater than the lattice constant of silicon, so that the corresponding epitaxially grown material may be formed in a strained state, thereby also exerting stress to the channel region 105 and thus creating a respective compressive strain therein. Selective epitaxial growth techniques for depositing silicon/germanium alloy materials are well established in the art and may be performed on the basis of appropriately selected process parameters, such as temperature, pressure, flow rate of precursor gases and carrier gases in such a manner that a significant deposition of material is substantially restricted to the crystalline silicon surfaces, while a deposition on dielectric materials may be suppressed. Moreover, during the deposition of the silicon/germanium material, a desired dopant species may also be incorporated into the deposition atmosphere, such as boron, in order to obtain a desired base doping for drain and source regions, depending on the required complexity of the vertical and lateral profile of the drain and source regions. Generally, a reduced series resistance of the drain and source regions may be achieved by providing high dopant concentrations, while, on the other hand, for highly scaled semiconductor devices, the corresponding electric field generated across the channel region 105 may result in increased charge carrier injection into the gate insulation layer 104A at high dopant concentrations, thereby typically requiring a reduced dopant concentration and a shallow profile of the drain and source regions in the vicinity of the gate electrode structure 104.
FIG. 1b schematically illustrates the transistor 100 in a further advanced manufacturing stage, in which the silicon/germanium alloy 109 may be formed in the cavities 106, as explained above, and wherein the spacers 107 and the cap layer 108 may be removed to expose the gate electrode structure 104. It should be appreciated that the spacers 104B may also be removed and may be replaced by appropriately designed offset spacers, if desired. As explained above, upon reducing the transistor dimensions, i.e., the gate length of the transistor 100, which is to be understood as the horizontal dimension of the gate electrode structure 104 in FIG. 1b, controllability of the channel region 105 may become increasingly difficult due to the short channel effects which, in some conventional approaches, may be countered in part by providing counter-doped regions 110, which may also be referred to as halo regions, in which the dopant concentration of the channel region 105 and the remaining semiconductor region, also referred to as the body region 102A, is significantly increased, thereby adjusting the inter gradient at corresponding PN junctions to be formed by providing shallow doped drain and source regions. Typically, the counter-doped regions or halo regions 110 may be formed by ion implantation, for instance using a tilt angle, in order to establish a certain degree of overlap with the gate electrode structure 104. However, upon further scaling the transistor dimensions, the dopant concentration and thus implantation dose may also have to be increased, thereby also increasing dopant-induced charge carrier scattering, dopant diffusion and, due to the high dose implantation processes involved, stress relaxation in the vicinity of the channel region 105. Furthermore, a dopant concentration in the drain and source regions is generally increased in order to obtain a reduced series resistance of the drain and source regions for not limiting device performance, also dose and energy for the implantation process for creating the halo regions 110 has to be increased. This in turn may further increase stress relaxation in the silicon/germanium alloy due to increased lattice damage and higher dopant diffusion. During the sophisticated implantation processes, longer treatment times may be required to obtain the desired high dose during the creation of the halo regions 110. Thus, although the silicon/germanium material 109 may be provided with high intrinsic dopant concentration, nevertheless, sophisticated and long implantation processes may be required for adjusting the PN junctions in the vicinity of the gate electrode structure 104 on the basis of the halo regions 110.
FIG. 1c schematically illustrates the transistor 100 according to further conventional approaches in an attempt to provide enhanced channel control and reduced dopant diffusion. As illustrated, the transistor 100 may comprise a spacer structure 111 including at least a first spacer element 111A and a second spacer element 111B, which may be separated by an etch stop liner (not shown), if required. Furthermore, the drain and source regions 112 may have a sophisticated profile in the lateral and vertical directions, wherein a very shallow portion 112A may connect to the channel region 105 and may have a concentration so as to provide enhanced channel control while avoiding an acceptable high electrical field strength in the vicinity of the gate electrode structure 104. Furthermore, an intermediate portion 112B is provided that has an increased dopant concentration due to the lateral offset to the channel region 105. Finally, a highly doped deeper drain and source portion 112C may be provided, in which an even increased dopant concentration may provide the required low resistance path in the drain and source regions 112. The sophisticated profile of the drain and source regions 112 as shown in FIG. 1c may be established by ion implantation processes in which the spacer structure 111 at the various manufacturing stages may be used as an implantation mask so as to adjust the lateral offset of the respective portions 112A, 112B, 112C to the channel region 105. Although this approach may provide enhanced channel controllability and a low resistance path in the drain and source regions 112, sophisticated implantation processes may be required wherein, however, in combination with the provision of a silicon/germanium alloy, significant lattice damage may be created, thereby contributing to a significant stress relaxation, which may be less desirable with respect to increasing charge carrier mobility in the channel region 105.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.